1. Field of the Invention
The invention in general relates to fabrication of integrated circuits and more particularly to the structure and process of fabricating landing pads for contacts in such circuits.
2. Statement of the Problem
As is well-known, integrated circuits, sometimes called semiconductor devices, are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer, which wafer is subsequently sawed into hundreds of identical dies or chips. While integrated circuits are commonly referred to as "semiconductor devices" they are in fact fabricated from various materials which are either electrically conductive, electrically nonconductive, or electrically semiconductive. Silicon, the most commonly used semiconductor material, can be used in either the single crystal or polycrystalline form. In the integrated circuit fabrication art, polycrystalline silicon is usually called "polysilicon" or simply "poly", and shall be referred to as such herein. Both forms of silicon may be made conductive by adding impurities to it, which is commonly referred to as "doping". If the doping is with an element such as boron which has one less valence electron than silicon, electron "holes" become the dominant charge carrier and the doped silicon is referred to as P-type silicon. If the doping is with an element such as phosphorus which has one more valence electron than silicon, additional electrons become the dominant charge carriers and the doped silicon is referred to as N-type silicon. Silicon dioxide is also commonly used in integrated circuits as an insulator or dielectric. Its use is so common that in the art is generally referred to as "oxide" without ambiguity.
CMOS (Complimentary Metal Oxide Semiconductor) technology is currently the most commonly used integrated circuit technology, and thus the present invention will be described in terms of silicon-based CMOS technology, although it is evident that it will find uses in other integrated circuit technologies. The term CMOS is now loosely applied to mean any integrated circuit in which both N-channel and P-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) are used in a complimentary fashion. CMOS integrated circuit fabrication may begin with a lightly-doped P-type silicon substrate, a lightly-doped N-type silicon substrate, or lightly-doped epitaxial silicon (deposited crystalline silicon) on a heavily doped substrate. For the sake of simplicity, the invention will be described using lightly-doped P-type silicon as the starting material, although it may be implemented with other materials as the starting point. If other materials are used as the starting point, there may be differences in materials and structure as is well-known in the art, e.g. with N-type silicon as the starting point dopant types may be reversed, or P-type wells may be introduced.
The advantages of building integrated circuits with smaller individual circuit elements so that more and more circuitry may be packed on a single chip are well-known: electronic equipment becomes less bulky, reliability is improved by reducing the number of solder or plug connections, assembly and packaging costs are minimized, and improved circuit performance, in particular higher clock speeds. However, the smaller the size, the more difficult it is to fabricate and locate individual parts, such as contacts, within the specifications and tolerances required. SRAM (Static Random Access Memory) is one of the most densely-packed integrated circuits commonly manufactured today. Thus the problems associated with small size are especially acute in SRAM.
An area in a integrated circuit to which electrical connection is to be made is generally called an active area (AA). Current integrated circuit technology often includes an intermediate doped semiconductor layer between an AA and the metal contact which connects the active area to an electrical source. This intermediate layer is called a contact landing pad or landing pad. In memories and other structures requiring densely packed contacts, landing pads are conventionally fabricated by creating a photolithographic mask containing the pattern of the parts to be fabricated, coating the wafer with a light-sensitive material called photoresist or resist, exposing the resist-coated wafer to ultraviolet light through the mask to soften or harden parts of the resist depending on whether positive or negative resist is used, removing the softened parts of the resist, etching the wafer to remove the part unprotected by the resist, and stripping the remaining resist. In each of these steps from mask, to photoresist, to etched wafer, critical dimension loss (CD loss) may occur. For example, in CMOS 4M SRAM with 0.8 .mu.m contacts and 0.2 .mu.m misalignment tolerance, a typical landing pad must be 1.2 .mu.m.times.1.2 .mu.m. When CD loss due to the etch of the landing pad material is factored in, the CD in resist may go to 1.4 .mu.m.times.1.4 .mu.m, assuming 0.1 .mu.m loss per edge. In a cell requiring 1.8 .mu.m contact pitch, this leaves a 0.4 .mu.m space between landing pads. This is very difficult with some conventional steppers Thus there is a need for a structure and fabrication process that can provide landing pads large enough to handle the required contacts that can be fabricated close enough together to meet the contact pitch requirements for state-of-the-art SRAM, and yet can be consistently fabricated with conventional steppers.
The business of fabricating semiconductor devices is a very competitive, high-volume business. Thus manufacturing efficiency is highly important. Product quality and reliability are also highly important. It is well-known in the art that increasing the number of levels in the integrated circuit not only increases manufacturing costs and time but also generally decreases the quality and reliability of the end product, since the opportunities for disabling defects to occur are increased. This in turn feeds back into further increased manufacturing costs since scrapped product is increased at the same time as the cost of individual scrapped pieces is increased. Thus, a structure and process that not only permits small contact pitch landing pads to be fabricated with conventional equipment, but also does not add to the number of levels in the fabrication process, would therefore be highly desirable.
3. Solution to the problem
The present invention provides an integrated circuit design in which two different levels in the fabrication process are "teamed" together to form the landing pads. The invention uses two fabrication levels or layers that may already be available in the integrated circuit fabrication process.
According to the invention first landing pad members are formed in one fabrication layer, and second landing pad members are formed in another layer. Each of the first landing pad members is smaller than the desired size for the whole landing pad, thus the members can be sufficiently separated so that they can be formed using conventional fabrication equipment. Likewise for the second landing pad members. The landing pad members are patterned so that each of the second landing pad members overlaps and "teams" with a first landing pad member to form the larger desired landing pad.